The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Semiconductor substrates often include features such as vias that are filled with a conductive material to allow interconnection of conductive layers. For example, some substrates may include an interlayer dielectric (ILD) arranged on a tungsten layer. A via may be defined in the ILD to allow connection to the tungsten layer. The via needs to be filled with a conductive material such as tungsten to allow connection to the tungsten layer. Usually, it is important for the connection to have low resistance to minimize power dissipation and heat.
A conformal fill approach may be used to fill the via. This approach grows tungsten film from both side walls of the via. As a dimension between the side walls shrinks, the tungsten grain growth is limited. As a result, the resistivity of the film is limited. Also, a seam can be created in a center of the via. The seam limits the volume filled with tungsten and compromises via resistance.